1. Technical Field
The present invention relates to an information storage medium on which is stored an interconnection program, an interconnection method, an interconnection apparatus, and a semiconductor device.
2. Related Art
When a current runs through a metal interconnect in an LSI, Joule heating always takes place because of collision of a conduction electron with a crystal lattice. The Joule heating increases the interconnect temperature, thereby increasing the resistance or accelerating electromigration. Accordingly, precise prediction of the life span of the LSI can only be made by accurately estimating the interconnect temperature taking the Joule heating into consideration. In order to assure the reliability of the LSI, it is essential to establish a model of the interconnect temperature increase due to the Joule heating, to thereby determine an appropriate limitation of the current with respect to the temperature increase.
For example, JP-A No. 2000-163460 discloses an interconnection method including calculating a current amount based on the load capacitance of the interconnect itself and the delay time of a cell, thereby evaluating the reliability. This document states that such method is also applicable to permissible current density, which is determined based on the criterion for limiting the heating value. Thus, the method determines a certain permissible current density, to thereby examine whether “current amount<interconnect width×permissible current density” is satisfied.
Meanwhile, the copper interconnect currently in popular use is generally manufactured through a Damascene process. This is a process including forming by etching a trench on an interlayer dielectric deposited in advance; depositing by physical vapor deposition a barrier metal for suppressing the diffusion of copper and a seed layer (Cu); and filling the trench with copper by plating or the like and grinding off the excessive layer by chemical mechanical polishing (hereinafter, CMP), thus forming the interconnect. To achieve sufficient flatness of the interconnect layer, it is necessary to evenly allocate the data rate, so that the interconnect layer can be uniformly ground in the wafer plane by the CMP process. For this purpose, generally a dummy interconnect, which is electrically isolated, is provided to thereby make the data rate as uniform as possible.
In addition to JP-A No. 2000-163460, the prior art related to the present invention includes JP-A No. 2005-346527, JP-A No. 2001-308156, and non-patent documents cited below.    [Patent document 1] JP-A No. 2000-163460    [Patent document 2] JP-A No. 2005-346527    [Patent document 3] JP-A No. 2001-308156    [Non-patent document 1] W. R. Hunter, “Self-Consistent Solutions for Allowed Interconnect Current Density—Part I: Implications for Technology Evolution”, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 44, No. 2, February 1997, pp. 304-309.    [Non-patent document 2] Ting-Yen Chiang et al., “Impact of Joule Heating on Scaling of Deep Sub-Micron Cu/low-k Interconnects”, 2002 Symposium on VLSI Technology Digest of Technical Papers, pp. 38-39.
The present inventors have recognized as follows. As stated above, in the typical interconnect based on the Damascene process, an interconnect involved in the Joule heating, i.e. an electrically active interconnect, and an interconnect not involved in the Joule heating, i.e. an electrically inactive interconnect, are mixedly laid out. Conventionally, however, the influence of the difference between the active and the inactive interconnects or the difference in data rate, which may act on the Joule heating, has not been taken into consideration. Therefore, a worst case, specifically the case where the electrically activated interconnect is most densely arranged, has to be assumed, which could lead to an excessively strict current limitation.